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  • Real-Time DSP Applications
  • 1. Overview
    • 1.1. Hardware Platform
    • 1.2. Software Development Tools
    • 1.3. Vitis Application Acceleration Development
  • 2. Introduction to HLS
    • 2.1. HLS Tasks
    • 2.2. Vitis HLS Development Flow
  • 3. HLS Design Basics
    • 3.1. Performance Metrics
    • 3.2. Producer-Consumer Model
    • 3.3. Deadlock
    • 3.4. Data Flow Graph Execution
  • 4. HLS Programming
    • 4.1. Functions
    • 4.2. Loops
    • 4.3. Arrays
    • 4.4. Math Data Types
  • 5. HLS Kernel Interface
    • 5.1. Global Memory Access
    • 5.2. Load-Compute-Store Pattern
  • 6. Host Programming
    • 6.1. OpenCL Basics
    • 6.2. OpenCL Steps
    • 6.3. OpenCL Optimization
  • 7. Filter Implementation
    • 7.1. Block Diagram & Signal Flow Graph
    • 7.2. FIR Filter
    • 7.3. IIR Filter
    • 7.4. Effects of Quantization
  • 8. Fast Fourier Transform
    • 8.1. Decimation-in-Time Algorithm
    • 8.2. Butterfly Structures
    • 8.3. HLS Implementation
    • 8.4. Effects of Quantization
  • 9. ADC as Signal Source
    • 9.1. Sampling Theorem
    • 9.2. ADC Interface
  • 10. References
  • Repository
  • Open issue

Index

A | B | C | F | I | P | R | S | V

A

  • Array Partitioning
  • Array Reshaping

B

  • block

C

  • complete
  • cyclic

F

  • FIFO

I

  • Imperfect loop nests

P

  • Perfect loop nests
  • PIPO
  • Processing System (PS):
  • Programmable Logic (PL):

R

  • RF System:

S

  • Semi-perfect loop nests

V

  • Vitis
  • Vitis HLS
  • Vivado

By Tan F. Wong

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